Embodiments of the present invention relate to semiconductor process control, reliability and testing. More particularly, embodiments of the present invention provide a method of detecting and distinguishing stack gate edge defects at the source or drain junction.
Flash memory is a type of semiconductor computer memory with many desirable characteristics. Like read only memory, ROM, it is non-volatile, meaning that the contents of the memory are stable and retained without applied electrical power.
A major advantage of flash over ROM is that the memory contents of flash may be changed after the device is manufactured. However, flash memory generally can not be written to, or programmed, at rates comparable to random access memory, RAM. Further, flash generally must be erased, either in its entirety or in large segments called pages, prior to changing its contents.
Flash memory has found wide acceptance in many types of computers, including desktop computers, mobile phones and hand held computers. Flash memory is also widely used in digital cameras and portable digital music players, for example xe2x80x9cMP3xe2x80x9d players.
In addition to direct flash storage applications, for example in video cameras, flash-based storage devices are replacing rotating magnetic disks, sometimes known as hard drives, in many applications. Compared to hard drives, flash is significantly more rugged, quieter, lower power, and for some densities such a flash based device may be smaller than a comparable hard drive.
As discussed above, a page of flash memory generally must be erased before new data may be stored in that page. Erasing a page is generally a long process, typically measured in hundreds of milliseconds. This is a disadvantage compared to RAM and hard drives, which may be written directly, without an interposing erasure.
For reasons of cost improvement, increasing speed of operation, power consumption decreases and other well known reasons, the semiconductor industry is pushing the semiconductor process geometry of flash memory devices to ever smaller sizes. A typical size of the smallest feature on a chip is, for example, 0.26 xcexcm. As flash memory devices are designed for this and smaller geometries, a xe2x80x9cchannelxe2x80x9d erase scheme is necessary for NOR-type flash devices. With channel erasure at such small process geometries, erase currents flow not only through the channel of the semiconductor device, but also through source and drain edges.
In an ideal case, erasure is controlled by the channel region device. Unfortunately, imperfections in the semiconductor manufacturing process may lead to defects in the stack gate edge. Such defects may occur, for example, in process steps such as stack gate etch, Self-Aligned-Source (SAS) and reverse SAS. There may be over 100 process steps involved; some may affect the source, while others may affect the drain. Such defects may in turn lead to erratic and/or fast erase bits in an array of flash memory cells. Consequently, it is critical to identify the location of such defects.
A widely used, well known industry standard inspection method is to examine sections of a semiconductor wafer with a tunneling electron microscope, TEM, to measure the thickness of the various layers, for example, polysilicon, oxide, metalization, etc. Unfortunately, stack gate errors may occur in any cell within an integrated circuit. Inspect of such defects with a TEM requires pre-knowledge of their location, and hence another means of detection. In addition, it is generally very difficult to slice the cross section in exactly the right spot, e.g., a single flash memory cell, to actually inspect such a defect. Consequently, TEM is generally of no value in inspecting semiconductors for stack gate defects.
What is highly sought in the industry, then, is a fast, non-destructive method of testing flash memory devices for stack gate defects.
A method and apparatus for testing semiconductors comprising stacked floating gate structures are disclosed. A floating gate is programmed. An electrical stress or disturb voltage is applied to a control gate with a source and a drain in a specific set of conditions. Subsequent to the stressing, a drain current versus gate voltage relationship is measured. The sequence of programming, stressing and measuring may be repeated with different conditions for source and drain. More particularly, positive and negative biases are applied to a source while a drain is held at ground, and similar biases are applied to a drain while a source is held at ground. Through inspection of the measurement information taken after this sequence of stress applications, a stack gate edge defect may be identified as associated with a source edge or a drain edge. In this novel manner, stack gate edge defects may be identified and localized via non-destructive means, and corrective actions to the semiconductor manufacturing process and/or the partially manufactured wafer may be taken.